A TDM transmitter multiplexes, in the time domain, several low speed parallel data channels into a single high speed serial data stream, referred to as the multiplexed data stream. The multiplexing operation uses a local high frequency clock signal synthesized from a local low frequency reference clock. The high speed serial data stream is then transmitted through a single transmission medium such as a coaxial cable or an optical fiber. Circuits used to perform the multiplexing operation in the time domain are commonly known as time division multiplexer circuits, or time division multiplexers.
Time division multiplexers are also used in test equipment, generally to generate high speed pseudo-random bit streams for laboratory evaluation of circuits and transmission systems. Usually, time division multiplexers used in TDM transmission systems operate at a single data rate, while those used in test equipment are preferably frequency agile.
When the multiplexed data are Non-Return-to-Zero (NRZ) coded, the local clock signals, used to perform the different data time multiplexing operations, have frequencies equal to sub-rates of the serial data and the highest clock frequency required is equal to half the serial data rate. When the highest frequency of the local clock signal is equal to half the serial data rate, time division multiplexers are known as half-rate clock time division multiplexers.
Half-rate clock time division multiplexers have a major drawback related to the duty cycle distortion of the half-rate clock, which directly impacts the multiplexed data duty cycle distortion, which in turn may significantly degrade the quality of a transmission.
Consequently, a full-rate local clock (meaning that the clock frequency is equal to the multiplexed data rate) retiming circuit is often used as a final stage of the time division multiplexer to suppress the multiplexed data duty cycle distortion due to the half-rate clock duty cycle distortion. The full-rate clock retiming circuit processes the multiplexed data using a single edge of the full-rate clock whereas the final multiplexing operation uses both edges of the half-rate clock. Thus, as opposed to the half-rate clock, the duty cycle distortion of the full-rate clock will not affect the data. On the other hand, the multiplexed data jitter accumulated during the multiplexing operation is being “reset” by the full-rate clock retiming circuit since all the sub-rate clocks are derived from the full-rate clock (assuming that the retiming circuit features a low enough jitter generation).
But time division multiplexers using a final full-rate clock retiming stage present a major difficulty in the form of time alignment between the full-rate clock and the multiplexed data. This alignment is strongly dependent on the propagation delay of the various building blocks of the time division multiplexer. The full-rate clock used to sample the multiplexed data in the final retiming circuit is also the clock used to derive the sub-rate clocks required for multiplexing the parallel data channels. The delay from the time the full-rate clock is divided to create the half-rate clock to the time the multiplexed data are presented to the final retiming stage input needs to be small enough (usually smaller than one full-rate clock period) for the retiming circuit to operate within its clock phase margin region, otherwise transmission errors will occur. This alignment issue is becoming more critical as the transmission data rate is rapidly increased, thus reducing the safe operating margins of the highest speed circuits in particular, such as the clock phase margin of the retiming circuit.
An existing solution commonly used to alleviate the full-rate clock and multiplexed data alignment issue is described in the article by Y. Nakasha et al., entitled “A 43 Gb/s Full-Rate-Clock 4:1 Multiplexer in InP-based HEMT Technology” International Solid-State Circuit Conference Digest, 2002, the disclosure of which is incorporated by reference herein. In this approach, the full-rate clock and/or the multiplexed data stream are delayed (using continuous or discrete delay adjustment elements) for the retiming circuit to operate within its clock phase margin region. But very often, the full-rate clock retiming circuit is already stressing the technology (which is used to implement the circuit) capabilities, and any additional circuitry (used for instance to adjust the clock and multiplexed data alignment) operating at the highest frequency may dramatically reduce the safe operating margins, reduce the overall performance and/or increase the power consumption. Moreover, since the delay elements have a limited delay tuning range, there will be a minimum data rate for which the delay will not cover a whole bit length of the multiplexed data and thus the retiming circuit may not operate within its clock phase margin. Also, the addition of these delay elements may significantly increase the data output jitter. This is especially true when the multiplexed data are delayed because of the pattern dependent jitter.
In view of the forgoing, there is a need for improved techniques which address the issue of final full-rate clock data retiming in a multiplexer circuit, especially when targeting high data rates which are already stressing the maximum frequency capabilities of existing technologies.